 SPICE Model
SPICE Model PDK
PDK Standard Cell
Standard Cell Design Environment
Design Environment Circuit Simulation
Circuit Simulation Circuit Analysis
Circuit Analysis Circuit Simulation
Circuit Simulation Standard Cell
Standard Cell Design & Verification
Design & Verification Parametric Testing
Parametric Testing Noise Measurement
Noise Measurement Integrated Testing
Integrated Testing 
         
                    
                    High-Sigma Yield Analysis Solution
Based on Primarius' unique technology of statistical modeling and high-sigma analysis algorithms
Performing circuit statistical simulation with non-destructive precision, as well as acceleration through efficient algorithms and parallelization
Improving designer productivity with the user-friendly GUI-based DFY (design for yield) environment called NDE (Nano Design Environment)
Based on the design goals, NDE allows users to run variation analysis, predict yield, access the effectiveness of yield and circuit optimization efforts, and improve product competitiveness
 
                        
                    Built-in SPICE engine &
high efficiency statistical algorithms
Fast PVT, Monte Carlo, 
advanced high-sigma analysis
Near-linear scaling 
on computer farm or public clouds
Validated with 
40nm/28nm/14nm/7nm/5nm process node
Most cost-effective 
parallelization licensing model
Friendly GUI for convenient viewing & 
processing of yield analysis results
High-sigma yield analysis
for memory and Standard Cell designs
Yield prediction and optimization
for analog and digital block designs
Foundries/IDMs technology development
for SRAM yield improvement
Fast PVT simulation
requiring numerous corners